The technique of the present disclosure relates to a semiconductor integrated circuit in which a protected circuit and a protective circuit that removes a surge generated in a power supply line of the protected circuit are formed in the same semiconductor substrate, and a manufacturing method thereof.
In general, for the semiconductor integrated circuit such as a large scale integrated circuit (LSI), the importance of protecting a circuit having a predetermined function (hereinafter, referred to as internal circuit or protected circuit) from a surge generated in a power supply line of the internal circuit is increasing along with microminiaturization and voltage decrease of the semiconductor integrated circuit.
As a representative example of the surge generated in the power supply line, an ESD surge, which suddenly raises the power supply line potential due to an electrostatic discharge (ESD) to an external terminal of the power supply line, is known.
For the purpose of preventing the internal circuit from being broken down when a high voltage pulse is generated at the external terminal due to the ESD surge, an element or a circuit for ESD protection is integrated in the semiconductor substrate together with the internal circuit (protected circuit).
As the element or the circuit for ESD protection, e.g. one using a diode, one using a grounded-gate metal oxide semiconductor (GGMOS) obtained by short-circuiting of the gate and the source, or one using a thyristor is utilized as a related art.
Many internal circuits have a complementary metal oxide semiconductor (CMOS) configuration. So, as a configuration having high process affinity with the internal circuit, there has been proposed an ESD protective circuit having a so-called RCMOS configuration using a CMOS circuit such as an inverter in addition to a detecting circuit using a resistor (R) and a capacitor (C) (refer to Japanese Patent Laid-open No. 2006-121007 (hereinafter, Patent Document 1) and C. A. Torres et al; “Modular, Portable, and Easily Simulated ESD Protection Networks for Advanced CMOS Technologies,” Electrical Overstress/Electrostatic Discharge Symposium, September 11-13. Symposium Proceedings, pp. 81-94, FIG. 1).
The circuit configuration of the ESD protective circuit having the RCMOS configuration is the same as that of FIG. 1, which relates to the disclosed technique of the present application.
An ESD protective circuit 1 shown in FIG. 1 is configured by connecting a resistive element R, a capacitive element C, a CMOS inverter circuit 4, and a protection MOS transistor 5 between a power supply line 2 and a ground line 3 as shown in the diagram.
Specifically, in the ESD protective circuit 1, the MOS transistor (hereinafter, protection MOS transistor) 5 that discharges a high voltage generated in the power supply line 2 attributed to an ESD to the ground line 3 is disposed between the power supply line 2 and the ground line 3. The drain and source of the protection MOS transistor 5 are connected to the power supply line 2 and the ground line 3, respectively. Furthermore, the resistive element R and the capacitive element C are connected in series between the power supply line 2 and the ground line 3 to configure an RC series circuit. In addition, the inter-element node is connected to the input of the CMOS inverter circuit 4 and the output of the CMOS inverter circuit 4 is connected to the gate of the protection MOS transistor 5.
This ESD protective circuit is so designed as not to react to normal potential rise and fluctuation of the power supply line by utilizing a time constant based on the resistive element R and the capacitive element C.
In the case of intentionally raising the potential of the power supply line like the case of normal power activation, the rising speed of the pulse is lower than that at the time of ESD surge generation. Therefore, a potential VRC of the node connecting the resistive element R and the capacitive element C rises up without a long delay from the rise of the potential of the power supply line.
In contrast, if a pulse with a frequency higher than that assumed in normal operation (e.g. ESD surge) is applied to the power supply line 2, the potential VRC of the node connecting the resistive element R and the capacitive element C in the RC series circuit rises up with a delay from the potential rise of the power supply line 2. The potential rise in the human body model (HBM), which is a representative model of the ESD, occurs in an extremely-short time of several hundreds of nanoseconds, and the time constant of the RC series circuit is so decided that the above-described potential VRC rises up with a delay from the potential rise of the power supply line 2 responding to the potential rise with such a high frequency.
If the potential VRC rises up with a delay from the rise of the potential of the power supply line, a positive pulse generated in the CMOS inverter circuit 4 is applied to the gate of the protection MOS transistor 5 for only the period until the potential VRC reaches the threshold value of the inverter of the CMOS inverter circuit 4.
Thus, the protection MOS transistor 5 is in the on-state for the time defined by this positive pulse to remove the ESD surge from the power supply line 2 to the ground line 3. Therefore, an internal circuit 6 connected between the power supply line 2 and the ground line 3 is protected from the ESD surge.
When the potential VRC reaches the threshold value of the inverter of the CMOS inverter circuit 4, the positive pulse applied to the gate of the protection MOS transistor 5 ends, and thus this transistor is immediately turned off.
In this manner, the ESD protective circuit having the RCMOS configuration detects the ESD surge by the detecting circuit (RC series circuit) using a resistor (R) and a capacitor (C) and immediately removes the ESD surge from the power supply line in response to the detection result by this detecting circuit.